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    Ken Choi, Ph.D. - Associate Professor

    Ken Choi, Ph.D.

    Associate Professor

    Office: Siegel Hall 318
    3301 South Dearborn Chicago, IL 60616

    Phone: 312.567.3461
    Fax: 312.567.8976
    Email: kchoi@ece.iit.edu
    Web: Personal Webpage
         

    Expertise

    • Ultra-Low-Power VLSI Design and Hardware Optimization for Multimedia Applications

    Education

    • Post Doctoral Research Associate, Sakurai Lab., University of Tokyo, 2005
    • Ph.D. ECE, Georgia Institute of Technology, 2003

    Research

    Dr. Ken Choi joined the department of Electrical and Computer Engineering at IIT in the fall of 2007. He was a senior CAD engineer and a technical consultant for ultra-low-power SOC (system-on-chip) design in Samsung and Sequence Design prior to joining IIT. His research interests include DFP (Design For Power) and DFM (Design for Manufacturing) for ultra-low-power VLSI chip design and automation, and circuit design for nanometer scaled devices such as Carbon Nanotube FETs.

    Honors/Awards

    Best Paper Award in 2010 International Symposium on Wireless Sensor Network and Technologies and Applications (WTA): Jaeik Cho, Ken Choi, et.al, “Simple Security Protocols Based on EPC Global Generation 2”, Dec., 12-15, 2011

    Best Paper Award in 2010 International Symposium on Wireless Sensor Network and Technologies and Applications (WTA): Li Li, Ken Choi, et. al., “Energy Efficient Encoder Design of Distributed Video Coding for Wireless Video Sensor Network”, Dec., 12-15, 2011

    Best Paper Award in 2010 International Symposium on Wireless Sensor Network and Technologies and Applications (WTA): Li Li and Ken Choi, “Activity Driven Optimized Bus Specific Clock Gating for Ultra-Low-Power Smart Applications”, Dec., 9-10, 2010

    Best Paper Award (LG Award) in 2010 IEEE International SoC Design Conference (ISOCC): Haiqing Nan and Ken Choi, “Novel Soft Error Hardening Design of Nanoscale CMOS Latch”, November, 22, 2010

    Best Paper Award (Cosar Award) in 2009 IEEE International SoC Design Conference (ISOCC): Haiqing Nan and Ken Choi, “Inter-Hierarchical Power Analysis Methodology to Reduce Multiple Orders of Magnitude Run-Time without Compromising Accuracy”, November, 24, 2009

    Current Projects

    Awards/Honors

    Patents

    Books

    Selected Publications

    1. Jaeik Cho, Taeshik Shon, Ken Choi, and Jongsub Moon, “Dynamic learning model update of hybrid-classifiers for intrusion detection,” The Journal of Supercomputing: Volume 64, Issue 2, p. 522-526, Mar. 2013
    2. Haiqing Nan and Kyuwon Choi, “TDDB Monitoring and Compensation Circuit Design for Deeply Scaled CMOS Technology,” IEEE Transactions on Device and Materials Reliability, Vol. 13, No.1, p. 18-25, Mar. 2013
    3. Li Li, Haiqing Nan and Ken Choi, “Activity Driven Fine-grained Clock Gating and Run Time Power Gating Integration,” IEEE Transactions on Very Large Scale Integration Systems (VLSI), TVLSI-00101-2011.R1, Vol. PP, Issue: 99, Mar. 2012
    4. Yu-Chi Tsao and K. Choi., “Area-Efficient VLSI Implementation for Parallel Linear Phase FIR Digital Filter of Odd Length Based on Fast FIR Algorithm,” IEEE Trans. on Circuits and Systems II. Vol. 59, Issue:6, p. 371-375, Jun.  2012
    5. Haiqing Nan and Ken Choi, “Low Cost and Highly Reliable Hardened Latch Design for Nanoscale CMOS Technology”, Elsevier Journal of Microelectronics Reliability, Vol. 52, Issue 6, P. 1209-1214, Jun. 2012
    6. Yuchi Tsao and Ken Choi, “Area-Efficient Parallel FIR Digital Filter Structures For Symmetric Convolutions Based on Fast FIR Algorithm,” IEEE Transactions on Very Large Scale Integration Systems (VLSI), ISSN: 366-371, Vol., 20, No.2, Feb. 2012
    7. Haiqing Nan and Ken Choi, “High Performance, Low Cost and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology”,  IEEE Trans. Circuits and Systems I, DOI 10.1109/TCSI.2011.2177135, Issue: 99, p.1-13, Jan. 2012
    8. Li Li and Ken Choi, “Activity Driven Optimized Bus Specific Clock Gating for Ultra-low-power Smart Space Applications,” IET Communications (Formerly IEE Communications), Vol 5, Issue 17, P. 2501-2508, Nov. 2011
    9. Kyung Ki Kim and Ken Choi, “Hybrid CMOS and CNFET Power Gating in Ultra-Low Voltage Design,” IEEE Transactions on Nanotechnology, Vol10, No 6, p.1439-1448, Nov. 2011
    10. Haiqing Nan, Ken Choi, “Novel Radiation Hardened Latch Design Considering Process, Voltage and Temperature Variations for Nanoscale CMOS Technology,” Elsevier Journal of Microelectronics Reliability, Vol. 51, P. 2086-2092, Aug. 2011
    11. Haiqing Nan, Kyungki Kim, Wei Wang, and Ken Choi, “Dynamic Voltage and Frequency Scaling for Power-Constrained Design using Process Voltage and Temperature Sensor Circuits,” Journal of Information Processing System, p. 93-102, Mar. 2011
    12. Kyung Ki Kim, Seong Mo Park, and K-w Choi, "On-Chip Aging Sensor Circuits for Reliable Nanoscale MOSFET Circuits", IEEE Transactions on Circuits and Systems II,  Vol. 57, Issue: 10, p. 798-802, Oct. 2010

    Professional Society Memberships