Ken Choi, Ph.D.
Assistant Professor
Office: Siegel Hall 318
3301 South Dearborn Chicago, IL 60616
Phone: 312.567.3461
Fax: 312.567.8976
Email:
kchoi@ece.iit.edu
Web:
Personal Webpage
Expertise
- DFP (Design For Power) VLSI chip design and automation for low power; and DFM (Design for Manufacturing) process variation and thermal effects analysis, and electrical verification for noise margin, IR drop, and signal EM (electro-migration).
Education
- Ph.D. ECE, Georgia Institute of Technology, 2003
- Post Doctoral Research Associate, Sakurai Lab., University of Tokyo, 2005
Research
Current Projects
Awards/Honors
Patents
Books
Selected Publications
K-w. Choi and A. Chatterjee, “Efficient Instruction-level optimization methodology for low-power embedded systems,” Proc. of ACM/IEEE International Symposium on System Synthesis, pp.147-152, Sept. 2001.K-w. Choi , Y. S. Dhillon, U. Diril, A. Chatterjee, et. al., "Power-Performance Trade-offs in Second Level memory used by as ARM-like RISC Architecture", Power Aware Computing, Kluwer Academic Publishers, Part IV, Chapter 11, pp 215-228, 2001.
K, Puttasuwami, K-w. Choi, A. Chatterjee, et. al, “System level power-performance trade-offs in embedded systems using voltage and frequency scaling of off-chip buses and memory,” Proc. of ACM/IEEE International Symposium on System Synthesis, Oct. 2002.
J.C. Park , K-w. Choi, A. Chatterjee, et. al, “Energy minimization of a pipelined processor using a low voltage pipelined cache,” Proc. of 36 th Annual Asilomar Conference on Signals, Systems, and Computers, Nov. 3-6, 2002.
K-w. Choi and A. Chatterjee, “HA 2TSD: Hierarchical time slack distribution for ultra-low power CMOS VLSI” Proc. of the International Symposium on Low Power Electronics and Design, pp.207-212, 2002 .
K-w. Choi and A. Chatterjee, “PA-ZSA (Power Aware Zero Slack Algorithm): A graph based timing analysis for ultra low-power CMOS VLSI,” Proc. of PATMOS’2002, pp. 178-187, Sep. 2002.
Y. S. Dhillon, U. Diril, K-w. Choi, and A. Chatterjee,"An O(n) supply voltage assignment for low-energy serially connected CMOS modules and a heuristic extension for acyclic data flow graphs", IEEE Computer Society Annual Symposium on VLSI, 2003.
K-w. Choi and A. Chatterjee, “UDSM (ultra deep submicron)-aware post-layout device and interconnect co-optimization for ultra low-power CMOS VLSI,” ISLPED, 2003.
K-w. Choi , Y. Xu, and T. Sakurai , “ Optimal Zigzag (OZ): a n e ffective yet f easible p ower- g ating s cheme a chieving t wo o rders of m agnitude l ower s tandby l eakage ,” in VLSI Sy mposium , Kyoto, Japan, 200 5 .
K-w. Choi , K.M. Choi and J.T. Kong, “Full-Chip-Level Considerations for Fine-Grained Power-Gating Scheme to Reduce Two Orders of Magnitude Lower Leakage Current,” in ISOCC 2005.
K-w. Choi and A. Chatterjee, “HiPOS: Hierarchical Power Optimization Strategy for ultra low-power CMOS VLSI,” submitted to IEEE Transactions of VLSI Systems.
K-w. Choi and A. Chatterjee, “Gate-level power-aware optimization via graph-based timing analysis for ultra low-power CMOS VLSI,” submitted to IEEE/ACM Transactions on Design Automation of Electronic Systems(TODAES).
K-w. Choi and Jerry Frenkil , “ VEDA: Vectorless Event-Driven Approach for Optimal Switch Sizing of Power-Gating Circuits to Reduce Two Orders of Magnitude of Leakage Power ,” in SAME conference in Nice, France, Oct., 2006.

