Erdal Oruklu

Education

Ph.D. CPE, Illinois Institute of Technology, Chicago, Illinois, 2005
M.Sc. EE, Bogazici University, Istanbul, Turkey, 1999
B.Sc. ECE, Technical University of Istanbul, Turkey, 1995

Research Interests

Dr. Oruklu joined the department of Electrical and Computer Engineering at IIT in May 2005. Dr. Oruklu's research interests are reconfigurable computing, advanced computer architectures, hardware/software co-design and embedded systems. The main focus of his studies is the research and development of system-on-a-chip (SoC) frameworks for FPGA and VLSI implementations of signal processing algorithms.

Dr. Oruklu will be teaching courses in the areas of VLSI design, computer architecture, embedded system design and signal processing architectures.

Publications

Oruklu E., and J. Saniie, High Speed Design and Performance Evaluation of Frequency-Diverse Orthogonal Transforms for Ultrasonic Imaging Applications, IEEE Symposium on Ultrasonics, Vol. 1, pp. 258-261, October 2003.

Oruklu E., and J. Saniie, Ultrasonic Flaw Detection Using Discrete Wavelet Transform for NDE Applications, IEEE Symposium on Ultrasonics, Vol. 2, pp. 1054-1057, August 2004.

Oruklu E., F. Martinez, and J. Saniie, A Reconfigurable Architecture for Target Detection in High Density Clutter Environments using Subband Decomposition Algorithms, Global Signal Processing Expo (GSPx) Technical Conference, October 2004.

Oruklu E, and J. Saniie, Performance Evaluation of Multiplierless Architectures for Frequency Diverse Target Detection Algorithms. IASTED International Conference on Circuits, Signals and Systems, November 2004.

Oruklu E, G. Cardoso, and J. Saniie, Reconfigurable Architecture for Ultrasonic Signal Compression and Target Detection, IEEE International Conference on Acoustics, Speech, and Signal Processing, Vol. 5, pp. 129-132, March 2005.

Martinez F., E Oruklu, and J. Saniie, A Distributed Processing Network Architecture for Reconfigurable Computing, IEEE Electro-Information Technology Conference 2005, May 2005.

Martinez F., E. Oruklu, and J. Saniie, Dynamic Reconfigurable Distributed Distributed Processing Network with Dual Levels of Operand Granularity, IEEE Midwest Symposium on Circuits and Systems, Vol. 2, pp. 1211-1214, August 2005.

Oruklu E, and J. Saniie, Efficient Hardware Realization of Frequency-Diverse Ultrasonic Flaw Detection using Zero-Phase IIR Filters, IEEE Symposium on Ultrasonics, Vol. 3,pp. 1785 - 1788, September 2005.

Oruklu E., and J. Saniie, Hardware Efficient Realization of a Real-Time Ultrasonic Target Detection System, under revision for IEEE Transactions on Ultrasonics, Ferroelectrics and Frequency Control, June 2006.

Oruklu E., and J. Saniie, Dynamically Reconfigurable Architecture Design for Ultrasonic Imaging, under revision for IEEE Transactions on Circuits and Systems, July 2006.

Dave V., E. Oruklu, and J. Saniie, Performance Evaluation of Flagged Prefix Adders for Constant Addition, IEEE Electro-Information Conference, May 2006.

Dave V., E. Oruklu and J. Saniie, Design and Synthesis of Flagged Binary Adders with Constant Addition, IEEE Midwest Symposium on Circuits and Systems, August 2006.

Oruklu E. and J. Saniie, Real-Time Ultrasonic Imaging System Based on Discrete Cosine Transform for NDE Applications, IEEE Symposium on Ultrasonics, October 2006.

Yoon S., E. Oruklu and J. Saniie, Dynamically Reconfigurable Neural Network Architectures for Ultrasonic Flaw Detection, IEEE Symposium on Ultrasonics, October 2006.

Lu Y., R. Demirli, E. Oruklu and J. Saniie, Estimation and classification of ultrasonic echoes backscattered from reverberant multilayered materials, ICU Ultrasonic Conference, accepted for publication, April 2007.

Oruklu E., S. Yoon and J. Saniie, Robust flaw detection for NDE applications using Neural Network architectures, ICU Ultrasonic Conference, accepted for publication, April 2007.

Moskal J., E. Oruklu and J. Saniie, Design and Synthesis of a Carry-Free Signed-Digit Decimal Adder, IEEE ISCAS 2007 accepted for publication, May 2007.

Dave V., Erdal Oruklu, and J. Saniie, Design and Synthesis of a Three-input Flagged Prefix Adder, IEEE ISCAS 2007 accepted for publication, May 2007.

Parta H., E. Oruklu and J. Saniie, Real-Time FPGA Implementation of a Reconfigurable Ultrasonic Detection System, accepted for publication, May 2007.

Xiao X., E. Oruklu and J. Saniie, Efficient FFT Engine with Reduced Addressing Logic, accepted for publication, May 2007.

Dave V., Erdal Oruklu, and Jafar Saniie, Performance Evaluation of Three-Input Flagged Prefix Adder, submitted to IEEE MWSCAS 2007, August 2007.

Oruklu E, Reconfigurable Signal Processing Architectures for Ultrasonic Imaging, Ph.D. Dissertation, Chicago, IL, May 2005.

Oruklu E, “Implementation of a Low-Bit Rate Video Codec”, MS Thesis, Istanbul, Turkey, 1999.

Expertise

Reconfigurable computing, advanced computer architectures, hardware/software co-design and embedded systems.